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Datasheet File OCR Text:

FUJITSU SEMICONDUCTOR DATA SHEET
DS07-08201-1E
Family
FR450 Series VLIW Embedded Microprocessor
MB93461
DESCRIPTION
MB93461 realizes excellent performance in the field by combining advanced general processing and media processing for Digital AV equipments such as Television, Advanced Projector, IP TV Phone, Portable Media Player, etc. The processor core embedded in MB93461 can combine maximum two instructions out of integer operation instruction, media instruction, and branch instruction and can issue them in units of VLIW (Very Long Instruction Word) instruction per cycle. Moreover, peripheral resource modules including MMU (Memory Management Unit) , SDRAM controller (SDRAMC) , interrupt controller (IRC) , DMA controller (DMAC) , asynchronous transfer module (UART) , TIMER/COUNTER, general-purpose input/output (GPIO) , video display controller (VDC) , video capture controller (VCC) , audio interface, serial interface (I2C*) , USB interface (Full Speed Host/Function) , Memory Stick interface, and SD-IO interface are embedded in MB93461. * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
PACKAGES
420-ball plastic BGA 400-ball plastic PFBGA
(BGA-420P-M25)
(BGA-400P-M04)
MB93461
FEATURES
FR450 CPU Core * 2-way VLIW Processor Core * Core Frequency : 400 MHz/360 MHz * MMU is embedded * Peak Performance (Core Frequency : 400 MHz) 800 MIPS (Integer operation performance) , 3200 MOPS + 400 MIPS (Media operation performance, 4MAC + Integer) * 64 32-bit registers (32GR + 32FR) Cache * Instruction cache 32 KB (2way) , line size 32 Byte * Data cache 32 KB (2way) , line size 32 Byte * Non-blocking cache (Data Cache) * 64-byte store buffer (Data Cache) SDRAM interface * SDRAM compliant with PC133 standard can be connected, Variable 32-bit/16-bit data bus and 4 CS Local bus interface * 32-bit address/32-bit, 16-bit, or 8-bit data * Directly connecting SRAM/ROM, etc. is possible JTAG * Boundary scan function compliant with IEEE1149.1 is supported AV peripheral resource * Video Display Controller (VDC) Scan method : progressive/interlace Horizontal resolution : 320 to 1920 pixels, Vertical resolution : 240 to 1200 pixels OSD display : Max 1920x1200 pixels , 255/15 colors + transparent * Video Capture Controller ( VCC ) Scan method : progressive/interlace Horizontal resolution : 320 to 1920 pixels, Vertical resolution : 240 to 1200 pixels Reduce Scaler * Audio output 3-line serial (SPD-IF, I2S, MSB-Justified) , PCM highway, and Digital volume are supported * Audio input 3-line serial (I2S, MSB-Justified) and PCM highway are supported * Serial interface (I2C, 2 channels) Standard transfer (100 Kbps) and high-speed transfer (400 Kbps) are supported * USB interface USB 2.0 FS Host/Function * MS1.4 Interface * SD-IO interface * AV-DMAC (8 channels) * GPIO (32-bit) (Continued)
2
MB93461
(Continued) General-purpose peripheral resource * Interrupt Controller (IRC) * DMAC (8 channels) * UART (2 channels) * Timer (3 channels) * GPIO (22-bit) Recommended operation condition and external shape * Power supply voltage and current Externally 3.3 V 0.15 V, Internally 1.4 V 0.07 V (at 400 MHz) , Internally 1.3 V 0.065 V (at 360 MHz) * Operating temperature range from 0 C to + 70 C
PRODUCT LINEUP
These specifications have indicated four kinds of following products. 1) MB93461PB-GE1 2) MB93461-40PB-GE1 3) MB93461BGL-GE1 4) MB93461-40BGL-GE1 Part number Core Frequency Voltage external/ internal Ta Package (code) Thermal resistance Rth (ja) Remarks BGA420 (BGA-420P-M25) 19 C/W (0 m/s) Lead-free Solder ball MB93461PB-GE1 360 MHz 3.3 V 0.15 V/ 1.3 V 0.065 V MB93461-40PB-GE1 400 MHz 3.3 V 0.15 V/ 1.4 V 0.07 V MB93461BGL-GE1 360 MHz 3.3 V 0.15 V/ 1.3 V 0.065 V MB93461-40BGL-GE1 400 MHz 3.3 V 0.15 V/ 1.4 V 0.07 V
0 C to + 70 C PFBGA400 (BGA-400P-M04) 42 C/W (0 m/s)
3
MB93461
PIN ASSIGNMENT
1. BGA420
64 pins from K10 to U17 are for thermal. Connect them to VSS.
INDEX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
1 100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
2 101 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 3 102 193 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 169 4 103 194 277 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 255 168 5 104 195 278 353 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406 405 404 333 254 167 6 105 196 279 354 7 106 197 280 355 8 107 198 281 356 9 108 199 282 357 10 109 200 283 358 11 110 201 284 359 12 111 202 285 360 13 112 203 286 361 14 113 204 287 362 15 114 205 288 363 16 115 206 289 364 17 116 207 290 365 18 117 208 291 366 19 118 209 292 367 20 119 210 293 368 21 120 211 294 369 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 403 332 253 166 402 331 252 165 401 330 251 164 400 329 250 163 399 328 249 162 398 327 248 161 397 326 247 160 396 325 246 159 395 324 245 158 394 323 244 157 393 322 243 156 392 321 242 155 391 320 241 154 390 319 240 153 389 318 239 152 388 317 238 151
22 121 212 295 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 316 237 150 23 122 213 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 236 149 24 123 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 148 25 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(BGA-420P-M25)
4
MB93461
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Position A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 T1 U1 V1 W1 Y1 AA1 AB1 AC1 AD1 AE1 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11
Pin name N.C. N.C. N.C. N.C. HPWREN VCG[0] VCG[5] VSS VCR[1] VCR[6] VCB[1] VCB[6] VDR[0] VDR[1] VDR[6] VDG[1] VDG[6] VDB[1] VDB[6] ENABLE VDE VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. VDD DDQ[2] DDQ[7] DDQ[9] DDQ[14] DCAS# DCS#[2]
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Position AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AE26 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 P26 N26 M26 L26 K26 J26 H26 G26 F26 E26
Pin name VSS DA[0] DA[1] DA[4] DA[9] DBA[1] DDQM[3] DDQ[17] DDQ[22] DDQ[25] DDQ[30] N.C. N.C. N.C. N.C. N.C. N.C. N.C. TRST# VSS PRST# CMODE[3] VDD D[2] D[7] D[10] D[15] D[16] D[19] D[24] D[27] BE[0] BCLKO A[5] A[8] A[13]
Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
Position D26 C26 B26 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 B2 C2 D2 E2 F2 G2 H2 J2
Pin name N.C. N.C. N.C. N.C. N.C. N.C. N.C. A[23] A[26] VSS BSTREQ# BSTACK# BS# CS#[1] CS#[6] PP[00] PP[01] PP[04] PP[09] PP[12] PP[17] PP[13] SDCMD VSS VDD N.C. N.C. N.C. N.C. N.C. N.C. VDD VDD VCG[4] VCVSYNC VCR[0] (Continued) 5
MB93461
Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142
Position K2 L2 M2 N2 P2 R2 T2 U2 V2 W2 Y2 AA2 AB2 AC2 AD2 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20
Pin name VCR[5] VCB[0] VCB[5] VCB[7] VDR[2] VDR[7] VDG[2] VDG[7] VDB[2] VDB[7] TOPFIELD DISABLE VDE N.C. N.C. N.C. N.C. SDA[1] VSS DDQ[1] DDQ[6] DDQ[8] DDQ[13] DWE# DCS#[1] DCLKFB DRAS# DA[2] DA[5] DA[10] DA[11] DDQ[16] DDQ[18] DDQ[23]
Pin No. 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
Position AE21 AE22 AE23 AE24 AE25 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 P25 N25 M25 L25 K25 J25 H25 G25 F25 E25 D25 C25 B25 B24 B23 B22 B21 B20 B19
Pin name DDQ[26] DDQ[31] TESTMODE N.C. N.C. N.C. N.C. TMS ED VDE CMODE[2] CLKIN D[1] D[6] D[9] D[14] D[17] D[20] D[25] D[28] BE[1] BE[3] A[6] A[9] A[14] A[16] N.C. N.C. N.C. N.C. A[22] A[25] A[30] IBW
Pin No. 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210
Position B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P3 R3 T3 U3 V3 W3 Y3
Pin name A[31] WE# CS#[0] CS#[5] CPUHOLD PP[02] PP[05] PP[10] PP[15] PP[20] PP[16] SDDAT[0] SDCKI USCKI UDM N.C. N.C. VDE VSS VDE VCG[3] VCHSYNC VDD VCR[4] VCR[7] VCB[4] VSS VDR[3] VDG[0] VDG[3] VDB[0] VDB[3] VDCLKOUT VDD (Continued)
6
MB93461
Pin No. 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 Position AA3 AB3 AC3 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 P24 Pin name FSCKI LRCKI SDO N.C. SDA[0] SCL[1] DDQ[0] DDQ[5] VDD DDQ[12] DDQ[15] DCS#[0] VSS DCS#[3] DA[3] DA[6] DBA[0] DA[12] VSS DDQ[19] DDQ[24] DDQ[27] VSS TDC N.C. TDO TDI ERST# RAMBOOT# CMODE[1] VSS D[0] D[5] D[8] D[13] Pin No. 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 Position N24 M24 L24 K24 J24 H24 G24 F24 E24 D24 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 D4 E4 F4 G4 Pin name D[18] D[21] D[26] D[29] BE[2] A[2] A[7] A[10] A[15] A[17] N.C. A[19] A[21] A[24] A[29] BREQ# VDE RD# BGNT# CS#[4] CS#[7] PP[03] PP[06] PP[11] PP[18] PP[21] SDCLK SDDAT[1] VDE VDD UDP VDE UDM1 VSS VCG[2] Pin No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 Position H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 V4 W4 Y4 AA4 AB4 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 Pin name VCG[7] VDE VCR[3] VDE VCB[3] VDE VDR[4] VSS VDG[4] VSS VDB[4] VDHSYNC VSS SDI BCKO VDE SCL[0] VDE DDQ[4] VDE DDQ[11] VDE DDQM[1] DCLK VSS VSS DA[7] VSS DCKE VDE DDQ[20] VSS DDQ[28] VDE MTESTMODE (Continued) 7
MB93461
Pin No. 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348
Position AB23 AA23 Y23 W23 V23 U23 T23 R23 P23 N23 M23 L23 K23 J23 H23 G23 F23 E23 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
Pin name TCK HRST# VSS CMODE[0] VSS RSTOUT# D[4] VDE D[12] VSS D[22] VSS D[30] VSS A[3] VSS A[11] VSS A[18] A[20] VDE A[28] ERR# VDD RDY# VDE CS#[3] VDE VSS PP[07] VSS PP[19] VSS
Pin No. 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378* 379 380 381
Position D8 D7 D6 D5 E5 F5 G5 H5 J5 K5 L5 M5 N5 P5 R5 T5 U5 V5 W5 Y5 AA5 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16
Pin name SDWP SDDAT[2] SDCD VSS UDP1 HOVRCUR# VCG[1] VCG[6] VCDCLKIN VCR[2] VSS VCB[2] VSS VDR[5] VDE VDG[5] VDE VDB[5] VDVSYNC VDPCLKIN BCKI LRCKO VSS DDQ[3] VSS DDQ[10] VSS DDQM[0] VDD VDD VDE DA[8] VDE
Pin No. 382 383 384 385 386 387 388 389 390 391* 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414
Position AB17 AB18 AB19 AB20 AB21 AB22 AA22 Y22 W22 V22 U22 T22 R22 P22 N22 M22 L22 K22 J22 H22 G22 F22 E22 E21 E20 E19 E18 E17 E16 E15 E14 E13 E12
Pin name DDQM[2] VDD DDQ[21] VDE DDQ[29] VDD ECV ECLK VDD VDD VDE D[3] VSS D[11] VDE D[23] VDE D[31] VDE A[4] VDE A[12] VDD VSS A[27] VDD VSS DIR VSS CS#[2] VSS VDE PP[08] (Continued)
8
MB93461
(Continued) Pin No. 415 416 417 418 419 420
Position E11 E10 E9 E8 E7 E6
Pin name VDE PP[14] VDD MSDIRP SDDAT[3] SDMSSELECT
* : Pin No. 378 and 391 are the analog power supply pins of PLL.
9
MB93461
2. PFBGA400
81 pins from L11 to W19 are for thermal. Connect them to VSS. (TOP VIEW)
INDEX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 14 17 18 19 20 21 22 23 24 25 26 27 28 29
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ
1 112 111 110 109 108 107 106 105 104 103 102 101 100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
2 113 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 3 114 217 312 311 310 309 308 307 306 305 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 190 4 115 218 313 400 399 398 397 396 395 394 393 392 391 390 389 388 397 386 385 384 383 382 381 380 379 288 189 5 116 219 314 6 117 220 315 7 118 221 316 8 119 222 317 9 120 223 318 10 121 224 319 11 122 225 320 12 123 226 321 13 124 227 322 14 125 228 323 15 126 229 324 16 127 230 325 17 128 231 326 18 129 232 327 19 130 233 328 20 131 234 329 21 132 235 330 22 133 236 331 23 134 237 332 24 135 238 333 25 136 239 334 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 378 287 188 377 286 187 376 285 186 375 284 185 374 283 184 373 282 183 372 281 182 371 280 181 370 279 180 369 278 179 368 277 178 367 276 177 366 275 176 365 274 175 364 273 174 363 272 173 362 271 172 361 270 171 360 269 170 359 268 169 358 267 168
26 137 240 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 266 167 27 138 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 166 28 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
(BGA-400P-M04)
10
MB93461
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Position A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 L1 M1 N1 P1 R1 T1 U1 V1 W1 Y1 AA1 AB1 AC1 AD1 AE1 AF1 AG1 AH1 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6
Pin name N.C. N.C. UDP1 HPWREN VDD VCG[3] VCG[7] VCDCLKIN VCR[1] VCR[5] VCR[7] VCB[3] VSS VDR[0] VDR[4] VDG[0] VDG[2] VDG[6] VDE VDB[4] VDCLKOUT TOPFIELD VDE BCKI BCKO N.C. N.C. N.C. N.C. N.C. SDA[1] VDD DDQ[1] DDQ[5]
Pin No. 35 36 37 38 39 40 41* 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Position AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AH29 AG29 AF29 AE29 AD29 AC29 AB29 AA29 Y29 W29 V29
Pin name VDE DDQ[10] DDQ[14] DWE# DCS#[0] DCLK VDD DA[0] VSS DA[6] DA[10] DBA[1] DDQM[2] VDE DDQ[19] DDQ[23] DDQ[25] DDQ[29] VDE TDC N.C. N.C. N.C. N.C. TCK ECV VSS VDE CMODE[1] VSS VDE D[2] D[6] D[8]
Pin No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102
Position U29 T29 R29 P29 N29 M29 L29 K29 J29 H29 G29 F29 E29 D29 C29 B29 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Pin name D[12] D[16] VDE D[22] D[26] D[28] BE[0] VDE A[3] A[7] A[9] A[13] VDD A[18] N.C. N.C. N.C. N.C. A[20] VSS A[26] A[30] BREQ# VDD DIR BS# CS#[0] CS#[4] VDE PP[01] VDE PP[07] PP[11] PP[15] (Continued) 11
MB93461
Pin No. 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135
Position A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 L2 M2 N2 P2 R2 T2 U2 V2 W2 Y2 AA2 AB2 AC2 AD2
Pin name PP[17] VDD SDWP SDDAT[1] SDCKI VDD UDM N.C. N.C. N.C. N.C. VDE VDD VDE VCG[2] VCG[6] VSS VCR[0] VCR[4] VDE VCB[2] VCB[6] VCB[7] VDR[3] VDR[7] VDG[1] VDG[5] VSS VDB[3] VDB[7] ENABLE VDPCLKIN SDI
Pin No. 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Position AE2 AF2 AG2 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AG28 AF28 AE28
Pin name LRCKI SDO N.C. N.C. SDA[0] VSS DDQ[0] DDQ[4] VSS DDQ[9] DDQ[13] DDQ[15] DDQM[1] VDD VSS DRAS# DA[3] DA[5] DA[9] VDE DCKE VSS DDQ[18] DDQ[22] VDE DDQ[28] VSS TESTMODE N.C. N.C. TDO TRST# ED
Pin No. 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201
Position AD28 AC28 AB28* AA28 Y28 W28 V28 U28 T28 R28 P28 N28 M28 L28 K28 J28 H28 G28 F28 E28 D28 C28 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18
Pin name RAMBOOT# CMODE[0] VDD VDD D[1] D[5] VDE D[11] D[15] VSS D[21] D[25] D[27] D[31] VSS A[2] A[6] A[8] A[12] VSS A[17] N.C. N.C. A[19] A[23] A[25] A[29] ERR# VSS BSTACK# WE# BGNT# CS#[3] (Continued)
12
MB93461
Pin No. 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235
Position B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P3 R3 T3 U3 V3 W3 Y3 AA3
Pin name VSS PP[00] VSS PP[06] PP[10] PP[12] PP[14] VSS SDCLK SDDAT[0] VSS SDMSSELECT VSS VDE N.C. N.C. VSS VSS VCG[1] VCG[5] VCVSYNC VDD VCR[3] VSS VCB[1] VCB[5] VSS VDR[2] VDR[6] VDE VDG[4] VDB[0] VDB[2] VDB[6]
Pin No. 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269
Position AB3 AC3 AD3 AE3 AF3 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AF27 AE27 AD27 AC27
Pin name VDVSYNC VSS FSCKI VDE LRCKO VDE SCL[1] VDE DDQ[3] DDQ[7] DDQ[8] DDQ[12] VDE DDQM[0] DCS#[2] DCLKFB DCS#[3] DA[2] DA[4] DA[8] VSS DA[12] DDQ[16] DDQ[17] DDQ[21] VSS DDQ[27] DDQ[31] VDD MTESTMODE TMS ERST# VSS VDD
Pin No. 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303
Position AB27 AA27 Y27 W27 V27 U27 T27 R27 P27 N27 M27 L27 K27 J27 H27 G27 F27 E27 D27 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13
Pin name CMODE[3] CLKIN D[0] D[4] VSS D[10] D[14] D[18] D[20] D[24] VDE D[30] BE[2] BE[3] A[5] VDE A[11] A[15] A[16] N.C. A[22] A[24] A[28] VDD BSTREQ# A[31] RD# VDE CS#[2] CS#[6] CPUHOLD PP[03] PP[05] PP[09] (Continued) 13
MB93461
(Continued) Pin No. 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337
Position C12 C11 C10 C9 C8 C7 C6 C5 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 V4 W4 Y4 AA4 AB4 AC4 AD4 AE4 AF4 AF5 AF6
Pin name VDE PP[19] PP[21] PP[16] SDCMD SDDAT[3] SDCD VDD UDP UDM1 HOVRCUR# VCG[0] VCG[4] VCHSYNC VDE VCR[2] VCR[6] VCB[0] VCB[4] VDE VDR[1] VDR[5] VSS VDG[3] VDG[7] VDB[1] VDB[5] VDHSYNC VDD VDCDISABLE VSS SCL[0] VSS DDQ[2]
Pin No. 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371
Position AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AE26 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 P26 N26 M26
Pin name DDQ[6] VDD DDQ[11] VSS DCAS# DCS#[1] VSS VSS DA[1] VDE DA[7] DBA[0] DA[11] DDQM[3] VDD DDQ[20] DDQ[24] DDQ[26] DDQ[30] TDI HRST# ECLK PRST# CMODE[2] VSS RSTOUT# D[3] D[7] D[9] D[13] D[17] D[19] D[23] VSS
Pin No. 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400
Position L26 K26 J26 H26 G26 F26 E26 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
Pin name D[29] BE[1] BCLKO A[4] VSS A[10] A[14] A[21] VDE A[27] VSS IBW VDE RDY# VSS CS#[1] CS#[5] CS#[7] PP[02] PP[04] PP[08] VSS PP[18] PP[20] PP[13] MSDIRP SDDAT[2] VDE USCKI
* : Pin No. 41 and 171 are the analog power supply pins of PLL. 14
MB93461
PIN DESCRIPTION
1. Format
Pin No. Pin name Direction Type BS Description
Pin name : Indicates name of external pin If several signals share the same pin, the names are separated by a slash (/) . "# " in a signal line name indicates "active low." Direction : Indicates I/O of signal with reference to LSI chip Input : Indicates pin for input signal to LSI chip Output : Indicates pin for output signal from LSI chip Input/output : Indicates pin for bidirectional signal Type : Indicates pin input/output circuit type Each symbol has the following meaning : Symbol SD TS PU PD OD Description Solid Drive Type of output pin. Normal output. The pin never becomes high impedance. Tri-State Type of output or input/output pin. The pin may become high impedance. Pull-up Type of input pin or input/output pin. A pull-up resistor is built into the circuit. Pull-down Type of input pin or input/output pin. A pull-down resistor is built into the circuit. Open-drain Type of output pin. The pin may become high impedance.
Note : Explains outline of function and relationship with other pins. BS : Indicates whether the target of boundary-scan or not.
15
MB93461
2. Local Bus Interface
Pin No. BGA 261 PFBGA 91 Pin name Direction Type BS Description Bus Request This signal inputs a bus release request from the bus master device. Bus Grant This signal indicates that the local bus is released.
BREQ#
Input
Yes
264 177 175 260 337 406 81 174 259 80 173 258 335 257 334 255 168 254 167 72 403 332 253 166 71 252 165 70 401 330 251
200 295 90 195 292 381 89 194 291 193 290 379 87 192 82 189 288 287 378 80 187 286 377 79 186 78 185 284 375 77 184
BGNT# A[31] A[30] A[29] A[28] A[27] A[26] A[25] A[24] A[23] A[22] A[21] A[20] A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2]
Output
SD
Yes
Input/ output
TS
Yes
Address A word address is output. When the local bus is released, this pin becomes input.
(Continued)
16
MB93461
Pin No. BGA 399 328 249 162 67 248 161 66 397 326 247 160 65 246 159 64 63 158 245 324 395 62 157 244 61 156 243 322 393 60 155 242 PFBGA 182 281 372 74 181 73 180 279 370 72 179 278 369 277 368 70 177 276 367 69 176 275 366 68 365 67 174 273 364 66 173 272
Pin name D[31] D[30] D[29] D[28] D[27] D[26] D[25] D[24] D[23] D[22] D[21] D[20] D[19] D[18] D[17] D[16] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
Direction Type
BS
Description
Input/ output
TS
Yes
Data This is the data bus; D[31] is MSB. When connecting a 16-bit slave device to this signal, connect it to D[31 : 16] (higher) . When connecting a 8-bit slave device to this signal, connect it to D[31 : 24] (higher) . If all of the CS# that allowed to assert are configured to 8-bit or 16-bit (by LCR0-7.BW) , D[15 : 00] are not driven.
(Continued)
17
MB93461
Pin No. BGA PFBGA
Pin name
Direction Type
BS
Description Byte Enable This specifies byte lanes for data transfer. The correspondence between this signal and the data bus when accessing the 32-bit slave device is shown below (The CS area can be set only to the big endian (LCRx.LE = 0) .) : BE[0] D [31 : 24] BE[1] D [23 : 16] BE[2] D [15 : 08] BE[3] D [07 : 00] BE[0 : 1] is used to access a 16-bit slave device; the correspondence between this signal and the data bus is shown below : 1) The CS area set to big endian (LCRx.LE = 0) BE[0] D [31 : 24] (higher byte) BE[1] D [23 : 16] (lower byte) 2) The CS area set to little endian (LCRx.LE = 1) BE[0] D [23 : 16] (higher byte) BE[1] D [31 : 24] (lower byte) BE[2] is used to access halfword address. BE[2] A[1] BE[0] is used to access a 8-bit slave device; the correspondence between this signal and the data bus is shown below : BE[0] D [31 : 24] BE[2 : 3] is used to access byte address. BE[2] A[1] BE[3] A[0] These pins become input when the bus is released. To access this LSI as the slave device when this bus is released, it must be treated as a 32-bit slave device. BE[0] must be pulled-down/pulled-up according to BE/#BE polarity (When RSTOUT# is asserted, the value of BE[0] is reflected in LGCR.BED) . Bus Cycle Start This is asserted for only 1 CLKIN cycle at the beginning of a bus cycle to indicate the start of the bus cycle. This pin is input when the bus is released. Read This pin is asserted during the second or later CLKIN cycles of read local bus cycles. This pin becomes high impedance when the local bus is released. (Continued)
68 163 250 164
75 373 282 283
BE[0]/BE#[0] BE[1]/BE#[1] BE[2]/BE#[2] BE[3]/BE#[3]
Input/ output
TS
Yes
85
94
BS#
Input/ output
TS
Yes
263
296
RD#
Output
TS
Yes
18
MB93461
Pin No. BGA PFBGA
Pin name
Direction
Type
BS
Description Write Enable This pin is asserted during a write cycles. It can be used as a strobe pulse for write data. This pin becomes high impedance when the bus is released. Direction Indicates transfer direction of D[31 : 00] pins L : input (read) , H : output (write) This pin becomes input when the bus is released. This LSI determines whether the local bus cycles that performed by external devices are reads or writes, based on the DIR signal. This pin becomes "L" when bus is idle. Ready This pin is in the input state while the bus is not released; the bus cycle completion notice is "input" from the slave device to this pin. This pin becomes output while this LSI is operating as the slave bus when the bus released; it notifies the bus master device of the bus cycle completion. When RSTOUT# is asserted, the value of RDY# is reflected in LCR0.RC. Error This is sampled at the end of the bus cycle; the error notice is input from the slave device to this pin. This pin is ignored when the bus is released. Chip Select This signal selects slave device under control of MB93461. The corresponding address is determined from the settings of the programmable address decoder built into MB93461. Connect the boot ROM to the CS#[0] pin. Chip Select/Interrupt Request 7-4 This signal is used as chip select or interrupt request. Chip select selects slave device under control of this LSI. This signal works as IRQ#[7 : 4] after power-on reset and need to set LGCR.CSE to use as CS#. When use as CS#, the corresponding address is determined from the setting of the programmable address decoder built into this LSI. (Continued) 19
178
199
WE#
Output
TS
Yes
409
93
DIR
Input/ output
TS
Yes
340
385
RDY#
Input/ output
TS
Yes
338
196
ERR#
Input
Yes
342 411 86 179
201 298 387 95
CS#[3] CS#[2] CS#[1] CS#[0]
Output
SD
Yes
266 87 180 265
389 299 388 96
CS#[7]/IRQ#[7] CS#[6]/IRQ#[6] CS#[5]/IRQ#[5] CS#[4]/IRQ#[4]
Input/ output
TS/ PU
Yes
MB93461
(Continued) Pin No. BGA PFBGA
Pin name
Direction Type
BS
Description Initial Bus Width This pin is used to specify the data bus width of the boot ROM to be connected to the CS#[0] pin. The data bus width specified for this signal can be changed later via software. 16 bits : Input low level 32 bits : Input high level Burst Request This pin is used to request burst transfer. Burst Acknowledge This pin is used to enable burst transfer. Bus Clock Out This clock is supplied to the device connected with the local bus. Output stops during power-on reset.
176
383
IBW
Input
Yes
83 84
294 198
BSTREQ# BSTACK#
Input/ output Input/ output
TS TS
Yes Yes
69
374
BCLKO
Output
SD
Yes
20
MB93461
3. SDRAM Interface
Pin No. BGA 224 36 133 222 42 227 228 139 138 41 380 307 226 137 40 225 136 39 38 135 35 132 309 PFBGA 252 250 343 39 46 349 257 350 45 154 255 348 44 153 254 152 253 346 42 151 342 38 156 Pin name Direction Type BS Description Chip Select This signal is output based on the setting of the programmable address decoder incorporated in this LSI. DCS#[2] and DCS#[3] are only used for connecting the 168-pin registered DIMM. Bank Address The bank address is output.
DCS#[3] DCS#[2] DCS#[1] DCS#[0] DBA[1] DBA[0] DA[12] DA[11] DA[10] DA[9] DA[8] DA[7] DA[6] DA[5] DA[4] DA[3] DA[2] DA[1] DA[0] DRAS# DCAS# DWE# DCKE
Output
SD
Yes
Output
SD
Yes
Output
SD
Yes
Multiplexed Address The address multiplexed for SDRAM is output.
Output Output Output Output
SD SD SD SD
Yes Yes Yes Yes
Row Address Strobe Row Address Strobe signal to SDRAM. Column Address Strobe Column Address Strobe signal to SDRAM. Write Enable Write Enable signal to SDRAM. Clock Enable Clock Enable signal to SDRAM. Data Mask These pins (signal) are combined with other signals to specify the byte lane to be written. At read, all the bits are driven Low. The correspondence between this signal and the data bus when connecting 32-bit SDRAM is shown below : DDQM[0] DDQ[31 : 24] DDQM[1] DDQ[23 : 16] DDQM[2] DDQ[15 : 08] DDQM[3] DDQ[07 : 00] The correspondence between this signal and the data bus when connecting 16-bit SDRAM is shown below : DDQM[0] DDQ[31 : 24] DDQM[1] DDQ[23 : 16] (Continued) 21
376 303 382 43
249 148 47 351
DDQM[0] DDQM[1] DDQM[2] DDQM[3]
Output
SD
Yes
MB93461
(Continued) Pin No. BGA 144 47 386 313 232 143 46 231 142 45 384 311 230 141 44 140 221 34 131 220 301 374 33 130 32 129 218 299 372 31 128 217 PFBGA 263 356 52 161 262 355 51 354 50 159 260 353 49 158 259 258 147 37 146 247 340 36 145 246 245 338 34 143 244 337 33 142
Pin name DDQ[31] DDQ[30] DDQ[29] DDQ[28] DDQ[27] DDQ[26] DDQ[25] DDQ[24] DDQ[23] DDQ[22] DDQ[21] DDQ[20] DDQ[19] DDQ[18] DDQ[17] DDQ[16] DDQ[15] DDQ[14] DDQ[13] DDQ[12] DDQ[11] DDQ[10] DDQ[9] DDQ[8] DDQ[7] DDQ[6] DDQ[5] DDQ[4] DDQ[3] DDQ[2] DDQ[1] DDQ[0]
Direction
Type
BS
Description
Input/ output
TS
Yes
Data This signal is connected to the SDRAM data bus; DDQ[31] is MSB. When connecting 16-bit SDRAM, connect it to DDQ[31 : 16] When the bus width is set to 16 bits by DCFG.BW, DDQ[15 : 00] is fixed to the high-impedance state.
304
40
DCLK
Output
SD
Yes
SDRAM Clock This is the output of the clock signal supplied to SDRAM. The output is halted while the PLL is halted. The output is also halted during a power-on reset. Feedback for SDRAM Clock To adjust the DCLK phase, feedback input to the PLL built into this LSI chip.
134
251
DCLKFB
Input
Yes
22
MB93461
4. General-purpose Peripheral Resource
Pin No. BGA 88 89 182 267 90 PFBGA 203 98 390 301 391 Pin name IRQ#[0]/PP[00] IRQ#[1]/PP[01] IRQ#[2]/PP[02] IRQ#[3]/PP[03] TOUT[0]/ GATE[0]/PP[04] TOUT[1]/ GATE[1]/PP[05] Direction Type BS Description Interrupt Request 0 to 3/GPIO 0 to 3 These pins are used as the interrupt input and as a general-purpose I/O port (GPIO) . Timer ch 0 Output/Timer ch 0 Gate/GPIO 4 This pin is used as the timer ch 0 pin and as a general-purpose I/O port (GPIO) . Timer ch 1 Output/Timer ch 1 Gate/GPIO 5 This pin is used as the timer ch 1 pin and as a general-purpose I/O port (GPIO) . UART ch 0 Receive Data/GPIO 6 This pin is used as the UART ch 0 receive data and as a general-purpose I/O port (GPIO) . UART ch 0 Transmit Data/GPIO 7 This pin is used as the UART ch 0 transmit data and as a general-purpose I/O port (GPIO) . UART ch 0 Clear To Send Signal/GPIO 8 This pin is used as the UART ch 0 CTS signal and as a general-purpose I/O port (GPIO) . UART ch 0 Request To Send Signal/GPIO 9 This pin is used as the UART ch 0 RTS signal and as a general-purpose I/O port (GPIO) . UART ch 1 Receive Data/GPIO 10 This pin is used as the UART ch 1 receive data and as a general-purpose I/O port (GPIO) . UART ch 1 Transmit Data/GPIO 11 This pin is used as the UART ch 1 transmit data and as a general-purpose I/O port (GPIO) . DMAC ch 0 Transfer Request/GPIO 12 This pin is used as the UART ch 0 transfer request and as a general-purpose I/O port (GPIO) . DMAC ch 0 Acknowledge/GPIO 13 This pin is used as the DMAC ch 0 transfer acknowledge signal and as a general-purpose I/O port (GPIO) . (Continued)
Input/ output
TS
Yes
Input/ output Input/ output
TS
Yes
183
302
TS
Yes
268
205
RXD[0]/PP[06]
Input/ output
TS
Yes
345
100
TXD[0]/PP[07]
Input/ output
TS
Yes
414
392
CTS#[0]/PP[08]
Input/ output
TS
Yes
91
303
RTS#[0]/PP[09]
Input/ output
TS
Yes
184
206
RXD[1]/PP[10]
Input/ output
TS
Yes
269
101
TXD[1]/PP[11]
Input/ output
TS
Yes
92
207
DREQ#[0]/PP[12]
Input/ output
TS
Yes
94
396
DACK#[0]/PP[13]
Input/ output
TS
Yes
23
MB93461
(Continued) Pin No. BGA PFBGA
Pin name
Direction
Type
BS
Description DMAC ch 0 Transfer Done/DMAC ch4 Transfer Request/GPIO 14 This pin is used as the DMAC ch 0 transfer end signal, as the DMAC ch 4 transfer request, and as a general-purpose I/O port (GPIO) . DMAC ch 1 Transfer Request/GPIO 15 This pin is used as the DMAC ch 1 transfer request and as a general-purpose I/O port (GPIO) . DMAC ch 1 Acknowledge/GPIO 16 This pin is used as the DMAC ch 1 transfer acknowledge signal and as a general-purpose I/O port (GPIO) . DMAC ch 1 Transfer Done/DMAC ch 5 Transfer Request/GPIO 17 This pin is used as the DMAC ch 1 transfer end signal, as the DMAC ch 5 transfer request, and as a general-purpose I/O port (GPIO) . DMAC ch 2 Transfer Request/GPIO 18 This pin is used as the DMAC ch 2 transfer request and as a general-purpose I/O port (GPIO) . DMAC ch 3 Transfer Request/GPIO 19 This pin is used as the DMAC ch 3 transfer request and as a general-purpose I/O port (GPIO) . DMAC ch 2 Transfer Acknowledge/DMAC ch 6 Transfer Request/GPIO 20 This pin is used as the DMAC ch 2 transfer acknowledge signal, as the DMAC ch 6 transfer request, and as a general-purpose I/O port (GPIO) . DMAC ch 3 Transfer Acknowledge/DMAC ch 7 Transfer Request/GPIO 21 This pin is used as the DMAC ch 3 transfer acknowledge signal, as the DMAC ch 7 transfer request, and as a general-purpose I/O port (GPIO) .
416
208
DONE#[0]/ DREQ#[4]/PP[14]
Input/ output
TS
Yes
185
102
DREQ#[1]/PP[15]
Input/ output
TS
Yes
187
307
DACK#[1]/PP[16]
Input/ output
TS
Yes
93
103
DONE#[1]/ DREQ#[5]/ PP[17]
Input/ output
TS
Yes
270
394
DREQ#[2]/PP[18]
Input/ output
TS
Yes
347
305
DREQ#[3]/PP[19]
Input/ output
TS
Yes
186
395
DACK#[2]/ DREQ#[6]/ PP[20]
Input/ output
TS
Yes
271
306
DACK#[3]/ DREQ#[7]/ PP[21]
Input/ output
TS
Yes
24
MB93461
5. ICE Interface
Pin No. BGA PFBGA Pin name Direction Type BS Description ESB Reset For the printed circuit board using the ICE, connect the connector intended for the ICE to this pin; for the printed circuit board not using the ICE, open this pin. Hard Reset This is the reset input dedicated to the ICE. This pin function is equivalent to reset by the debugger hardware reset command. Reset by this pin will not reset debug related settings, so this pin can be used for debugging the reset sequence, etc. When using this pin, connect the reset switch signal to this pin; when not using this pin, fix it to the High level. ESB Command Valid Command valid signal for ICE interface. For the printed circuit board using the ICE, connect the connector intended for the ICE to this pin; for the printed circuit board not using the ICE, open this pin. ESB Data Data I/O signal for ICE interface. For the printed circuit board using the ICE, connect the connector intended for the ICE to this pin; for the printed circuit board not using the ICE, open this pin. ESB Clock Clock signal (output) for ICE interface. For the printed circuit board using the ICE, connect the connector intended for the ICE to this pin; for the printed circuit board not using the ICE, open this pin.
238
267
ERST#
Input
PD
Yes
317
358
HRST#
Input
Yes
388
60
ECV
Input
PU
Yes
151
168
ED
Input/ output
TS/ PD
Yes
389
359
ECLK
Output
TS
Yes
25
MB93461
6. Reset-related Pin
Pin No. BGA PFBGA Pin name Direction Type BS Description Power-on Reset This is the level trigger initialization signal. Apply the L level to this pin for 16 CLKIN clock cycles or more. This pin is used to cause a power-on reset; it initializes all registers and sequencers except cache and GR/FR. Reset Output This signal is asserted during a power-on reset. The power-on reset operation is prolonged in the LSI until the oscillation stabilization wait time for the internal PLL has elapsed. Consequently, use this signal to detect that the power-on reset operation has been completed in the LSI. When HRST# is asserted with the ICE used, this signal (RSTOUT#) is asserted as in the power-on reset. RAM Boot A software reset can be caused by applying a Low level to this pin. When this signal and the PRST# pin are asserted simultaneously, the power-on reset operation is preferred. At a power-on reset, the level input to this pin is reflected in the SA bit of the register HSR0, and then the reset vector address is determined as shown below based on the SA bit. Low level : 0x00000000 High level : 0xFF000000
57
360
PRST#
Input
Yes
321
363
RSTOUT#
Output
SD
Yes
239
169
RAMBOOT#
Input
Yes
7. CPU Status
Pin No. BGA 181 PFBGA 300 Pin name CPUHOLD Direction Output Type SD BS Yes Description CPU Hold Signal indicating that CPU stops in hold state.
26
MB93461
8. Clock
Pin No. BGA 154 58 153 240 319 PFBGA 271 270 361 63 170 Pin name CLKIN CMODE[3] CMODE[2] CMODE[1] CMODE[0] Direction Input Type BS Yes Description Clock Input External clock are input to this pin. Clock Mode Determines operating frequency of each section in LSI.
Input
Yes
9. Pin Related to JTAG
Pin No. BGA 237 PFBGA 357 Pin name Direction Type BS Description Test Data Input This is the test data input pin. This signal is sampled on the rising edge of TCK. Test Data Output This is the test data output pin. This drives active when the ATP controller is the Shift-IR or Shift-DR state. This signal changes on the falling edge of TCK. Test Mode Select This is the test mode select pin. This signal is sampled on the rising edge of TCK. Test Clock This is the test clock pin. Test Reset This is the TAP controller asynchronous reset. This pin initializes the TAP controller. When not using the JTAG function on the printed circuit board, input the same signal as PRST# to this pin.
TDI
Input
PU
No
236
166
TDO
Output
TS
No
150
266
TMS
Input
PU
No
316
59
TCK
Input
PU
No
55
167
TRST#
Input
PU
No
10. Test
Pin No. BGA 145 234 315 PFBGA 163 54 265 Pin name TESTMODE TDC MTESTMODE Direction Input Input Input Type BS Yes No Yes Description Test Mode Input Fix it at Low level on the printed circuit board. Test Input Fix it at Low level on the printed circuit board. UlTEST MODE Input Fix it at Low level on the printed circuit board.
27
MB93461
11. VDC Pin
Pin No. BGA 114 15 362 287 204 113 14 13 116 17 364 289 206 115 16 205 PFBGA 127 230 325 15 126 229 324 14 328 18 129 232 327 17 128 16 Pin name VDR[7]/VDCR[7]/AVPP[23] VDR[6]/VDCR[6]/AVPP[22] VDR[5]/VDCR[5]/AVPP[21] VDR[4]/VDCR[4]/AVPP[20] VDR[3]/VDCR[3]/AVPP[19] VDR[2]/VDCR[2]/AVPP[18] VDR[1]/VDCR[1]/AVPP[17] VDR[0]/VDCR[0]/AVPP[16] VDG[7]/VDY[7]/VDX[7] VDG[6]/VDY[6]/VDX[6] VDG[5]/VDY[5]/VDX[5] VDG[4]/VDY[4]/VDX[4] VDG[3]/VDY[3]/VDX[3] VDG[2]/VDY[2]/VDX[2] VDG[1]/VDY[1]/VDX[1] VDG[0]/VDY[0]/VDX[0] VDB[7]/VDCX[7]/VDCB[7]/ AVPP[39] VDB[6]/VDCX[6]/VDCB[6]/ AVPP[38] VDB[5]/VDCX[5]/VDCB[5]/ AVPP[37] VDB[4]/VDCX[4]/VDCB[4]/ AVPP[36] VDB[3]/VDCX[3]/VDCB[3]/ AVPP[35] VDB[2]/VDCX[2]/VDCB[2]/ AVPP[34] VDB[1]/VDCX[1]/VDCB[1]/ AVPP[33] VDB[0]/VDCX[0]/VDCB[0]/ AVPP[32] Direction Type BS Description R component output/Cr component output/GPIO These pins are display video data output pins. In the RGB mode, the red component is output. In the 24-bit YC mode, Cr component is output. These pins are shared by GPIO unit and set as GPIO input setting after reset. G Component output/Y component output/YC multiplexed output These pins are display video data output pins. In the RGB mode, the green component is output. Also, in the 16-bit or 24-bit YC mode, the Y component is output. When 8-bit YC mode is selected, multiplexed pixel data is output.
Input/ output
TS
Yes
Output
TS
Yes
118 19 366 291 208 117 18 207
132 235 330 20 131 234 329 233
Input/ output
TS
Yes
B Component output/C component output/Cb component output/ GPIO These pins are display video data output pins. In the RGB mode, the blue component is output. In the 16-bit YC mode, the Cb component and the Cr component are time-shared and output. Moreover, in the 24-bit YC mode, Cb component is output. These pins are shared by GPIO unit and set as GPIO input setting after reset.
292
331
VDHSYNC/VDHSYNC#
Output
TS
Yes
Horizontal synchronous signal output This pin is for display synchronous signal output. Its polarity is programmable. Vertical synchronous signal output This pin is for display synchronous signal output. Its polarity is programmable. (Continued)
367
236
VDVSYNC/VDVSYNC#
Output
TS
Yes
28
MB93461
(Continued) Pin No. BGA PFBGA
Pin name
Direction
Type
BS
Description Vertical pixel clock input This pin inputs a basic clock to generate display pixel clock output. Display pixel clock output Pixel data is output in synchronization with this signal. Pixel output enable This signal shows that effective pixel data is output. Its polarity is programmable. Top field This pin shows that the top field is displayed. Its polarity is programmable. Video output disable When this signal is asserted, VDR[7 : 0]/VDCR[7 : 0], VDG[7 : 0]/VDY[7 : 0], VDB[7 : 0]/VDCX[7 : 0]/VDCB[7 : 0], VDHSYNC, VDVSYNC, and VDCLKOUT go in to the high-impedance state. However, ordinary operation continues inside.
368
134
VDPCLKIN
Input
Yes
209
21
VDCLKOUT
Output
TS
Yes
20
133
ENABLE/ENABLE#
Output
TS
Yes
119
22
TOPFIELD/TOPFIELD#
Output
TS
Yes
120
333
DISABLE
Input
Yes
29
MB93461
12. VCC Pin
Pin No. BGA 201 10 109 200 283 358 9 108 281 356 7 106 197 280 355 6 PFBGA 11 320 10 121 224 319 9 120 7 118 221 316 6 117 220 315 Pin name VCR[7]/VCCR[7]/AVPP[15] VCR[6]/VCCR[6]/AVPP[14] VCR[5]/VCCR[5]/AVPP[13] VCR[4]/VCCR[4]/AVPP[12] VCR[3]/VCCR[3]/AVPP[11] VCR[2]/VCCR[2]/AVPP[10] VCR[1]/VCCR[1]/AVPP[9] VCR[0]/VCCR[0]/AVPP[8] VCG[7]/VCY[7]/VCX[7] VCG[6]/VCY[6]/VCX[6] VCG[5]/VCY[5]/VCX[5] VCG[4]/VCY[4]/VCX[4] VCG[3]/VCY[3]/VCX[3] VCG[2]/VCY[2]/VCX[2] VCG[1]/VCY[1]/VCX[1] VCG[0]/VCY[0]/VCX[0] VCB[7]/VCCX[7]/VCCB[7]/ AVPP[31] VCB[6]/VCCX[6]/VCCB[6]/ AVPP[30] VCB[5]/VCCX[5]/VCCB[5]/ AVPP[29] VCB[4]/VCCX[4]/VCCB[4]/ AVPP[28] VCB[3]/VCCX[3]/VCCB[3]/ AVPP[27] VCB[2]/VCCX[2]/VCCB[2]/ AVPP[26] VCB[1]/VCCX[1]/VCCB[1]/ AVPP[25] VCB[0]/VCCX[0]/VCCB[0]/ AVPP[24] Direction Type BS Description R component input/Cr component input/GPIO These pins are capture video data input pins. In the RGB mode, the red component is input. In the 24bit YC mode, Cr component is input. These pins are shared by GPIO unit and set as GPIO input setting after reset. G Component input/Y component input/YC multiplexed input These pins are capture video data input pins. In the RGB mode, the green component is input. Also, in the 24-bit YC mode, the Y component is input. When 8-bit YC mode is selected, multiplexed pixel data is output.
Input/ output
TS
Yes
Input
Yes
112 12 111 202 285 360 11 110
125 124 227 322 12 123 226 321
Input/ output
TS
Yes
B component input/C component input/Cb component input/GPIO These pins are capture video data input pins. In the RGB mode, the blue component is input. Also, in the 16-bit YC mode, Cb component and Cr component are timeshared and input. Moreover, in the 24-bit YC mode, Cb component is input. These pins are shared by GPIO unit and set as GPIO input setting after reset.
198
317
VCHSYNC/VCHSYNC#
Input
Yes
Horizontal synchronous signal input This pin is a capture synchronous signal input pin. Its polarity is programmable. Vertical synchronous signal input This pin is a capture synchronous signal input pin. Its polarity is programmable. Capture pixel clock input This pin is a sampling clock for capture. The edge to use is programmable.
107
222
VCVSYNC/VCVSYNC#
Input
Yes
357
8
VCDCLKIN
Input
Yes
30
MB93461
13. Audio Pin
Pin No. BGA 213 PFBGA 137 Pin name SDO/DX Direction Output Type TS BS Yes Description Audio data output Audio serial data is output. LR clock output/CH0 synchronous signal LR clock is output when it is I2S and MSB-Justified output. Moreover, if it is output that supports PCM highway, CH0 synchronous signal FS0 is output. Bit clock output This pin is for bit clock output for audio input/ output. Input/output that supports PCM highway always operates in the master mode, therefore, MCLK output by MB93461 is used for input as well. Audio data input This pin is for audio serial data input. LR clock input/CH1 synchronous signal output In the case of I2S and MSB-Justified input, it becomes LR clock input. Moreover, in the case of input/output that supports PCM highway, CH1 synchronous signal FS1 is output. Bit clock input This pin is for the input of bit clock used for I2S and MSB-justified audio input. Basic clock input for audio output This pin is for the input of basic clocks (256fS/ 384fS/512fS/756fS) to generate bit clock of MSB-justified or I2S audio output, LR clock and MCLK, FS0 and FS1 at supporting PCM highway.
370
240
LRCKO/FS0
Output
SD
Yes
295
25
BCKO/MCLK
Output
SD
Yes
294
135
SDI/DR
Input
Yes
212
136
LRCKI/FS1
Input/ output
TS
Yes
369
24
BCKI
Input
Yes
211
238
FSCKI
Input
Yes
31
MB93461
14. USB/USB-Host
Pin No. BGA 276 PFBGA 312 Pin name Direction Input/ output Input/ output Type BS Description USB D+ signal This pin is for differential signal (+) of USB function. USB D- signal This pin is for differential signal (-) of USB function. USB clock input This pin inputs 48 MHz clock that is required by USB interface. USB D+ signal This pin is for differential signal (+) of USB host. USB D- signal This pin is for differential signal (-) of USB host. USB Over Current Detection This signal is asserted when over current occurs in the down stream. It is read to the Over Current Indicator of HcRhstatus. Over-Current mode is set by No Over Current Protection of HcRh Descriptor A and Over CurrentProtection Mode. In the Individual over-current mode, it is read into Port Over Current Indicator of HcRh Port Status. This pin must be pulled up on the printed circuit board if not used. USB Port Power Enable Global power to the USB port is controlled by this signal. When No Power Switching is set, this signal is always active.
UDP
TS
No
191
109
UDM
TS
No
190
400
USCKI
Input
Yes
353
3
UDP1
Input/ output Input/ output
TS
No
278
313
UDM1
TS
No
354
314
HOVRCUR#
Input
Yes
5
4
HPWREN
Output
SD
Yes
15. I2C Pin
Pin No. BGA 216 297 PFBGA 242 335 Pin name Direction Type BS Description I2C clock These pins are used for a clock signal of the I2C bus. SCL[0] corresponds to I2C ch 0; SCL[1] corresponds to I2C ch 1. I2C data These pins are used for data signals for the I2C bus. SDA[0] corresponds to I2C ch 0; SDA[1] corresponds to I2C ch 1.
SCL[1] SCL[0]
Input/output
OD
No
126 215
31 140
SDA[1] SDA[0]
Input/output
OD
No
32
MB93461
16. SD/MS Pin
Pin No. BGA PFBGA Pin name Direction Type BS Description Clock input for the SD/Memory Stick If both of SD and MS are not used, set this pin to the "H" level on the printed circuit board. Data direction output of SDDAT[0]/MSDIO[0] If both of SD and MS are not used, set this pin to the "H" level on the printed circuit board. Data direction output of SDDAT[3 : 1]/ MSDIO[3 : 1] If both of SD and MS are not used, set this pin open on the printed circuit board. SD/Memory Stick insertion/extraction detection signal If both of SD and MS are not used, set this pin to the "H" level on the printed circuit board. SD command I/O/Memory Stick bus state signal If both of SD and MS are not used, set this pin to the "H" level on the printed circuit board. Transfer clock output for SD/Memory Stick If both of SD and MS are not used, set this pin open on the printed circuit board. Data signal for SD/Memory Stick (at serial) If both of SD and MS are not used, set this pin to the "H" level on the printed circuit board. Data signal for SD/Memory Stick (at parallel) If both of SD and MS are not used, set this pin to the "H" level on the printed circuit board. SD/Memory Stick selection signal input If both of SD and MS are not used, set this pin to the "H" level on the printed circuit board.
189
107
SDCKI/ MSCKI
Input
Yes
349
105
SDWP/ MSDIRS
Input/ output
Yes
418
397
MSDIRP
Input/ output
Yes
351
310
SDCD/MSCD
Input
Yes
95
308
SDCMD/MSBS
Input/ output
SD
Yes
272
210
SDCLK/MSCLK
Output
SD
Yes
188
211
SDDAT[0]/MSDIO[0]
Input/ output
TS
Yes
419 350 273
309 398 106
SDDAT[3]/MSDIO[3] SDDAT[2]/MSDIO[2] SDDAT[1]/MSDIO[1]
Input/ output
TS
Yes
420
213
SDMSSELECT
Input
Yes
Note : Customers are advised to consult with our sales representatives, if you use SD or MS.
33
MB93461
PIN STATE
H L HiZ X A : Indicates high level : Indicates low level : Indicates high-impedance state : Indicates either high level or low level : Indicates output of clock
Note : Initial value : Indicates pin state immediately after power-on reset. The meaning of each symbol is given below : Pin Name BREQ# BGNT# A[31 : 2] D[31 : 0] BE[0 : 3]/BE#[0 : 3] BS# , RD# , WE# DIR RDY# ERR# CS#[3 : 0] CS#[7 : 4]/IRQ#[7 : 4] IBW BSTREQ# BSTACK# BCLKO DCS#[3 : 0] DBA[1 : 0] DA[12 : 0] DRAS# , DCAS# DWE# DCKE DDQM[0 : 3] DDQ[31 : 0] DCLK DCLKFB IRQ#[3 : 0]/PP[03 : 00] TOUT[0]/GATE[0]/PP[04] TOUT[1]/GATE[1]/PP[05] Initial state H HiZ HiZ HiZ HiZ HiZ HiZ H HiZ HiZ HiZ L H L X H H H H HiZ L HiZ HiZ HiZ Core sleep mode Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Bus sleep mode H X HiZ X H X HiZ H H or HiZ H HiZ Operation L X X L H L H HiZ Operation Operation Operation Operation PLL operation mode H X HiZ X H X HiZ H H or HiZ H HiZ L L X X L H L H HiZ Operation X or HiZ X or HiZ X or HiZ PLL stop mode H X HiZ X H X HiZ H H or HiZ H HiZ L L X X L H L H HiZ L X or HiZ X or HiZ X or HiZ (Continued)
34
MB93461
Pin Name RXD[0]/PP[06] TXD[0]/PP[07] CTS#[0]/PP[08] RTS#[0]/PP[09] RXD[1]/PP[10] TXD[1]/PP[11] DREQ#[0]/PP[12] DACK#[0]/PP[13] DONE#[0]/DREQ#[4]/PP[14] DREQ#[1]/PP[15] DACK#[1]/PP[16] DONE#[1]/DREQ#[5]/PP[17] DREQ#[2]/PP[18] DREQ#[3]/PP[19] DACK#[2]/DREQ#[6]/PP[20] DACK#[3]/DREQ#[7]/PP[21] ERST# , HRST# ECV ED ECLK PRST# RSTOUT# RAMBOOT# CPUHOLD CLKIN CMODE[3 : 0] TDI TDO TMS , TCK , TRST# TESTMODE , TDC , MTESTMODE VDR[7 : 0]/VDCR[7 : 0] /AVPP[23 : 16] VDG[7 : 0]/VDY[7 : 0]/VDX[7 : 0]
Initial state HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ L L L HiZ
Core sleep mode Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation HiZ L Operation X HiZ Operation Operation
Bus sleep mode Operation Operation Operation Operation Operation Operation X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ HiZ L Operation X HiZ X or HiZ X
PLL operation mode X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ HiZ L Operation X HiZ X or HiZ X
PLL stop mode X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ X or HiZ HiZ L Operation X HiZ X or HiZ X (Continued)
35
MB93461
Pin Name VDB[7 : 0]/VDCX[7 : 0]/ VDCB[7 : 0]/AVPP[39 : 32] VDHSYNC/VDHSYNC# VDVSYNC/VDVSYNC# VDPCLKIN VDCLKOUT ENABLE/ENABLE# TOPFIELD/TOPFIELD# DISABLE VCR[7 : 0]/VCCR[7 : 0]/ AVPP[15 : 8] VCG[7 : 0]/VCY[7 : 0]/VCX[7 : 0] VCB[7 : 0]/VCCX[7 : 0]/ VCCB[7 : 0]/AVPP[31 : 24] VCHSYNC/VCHSYNC# VCVSYNC/VCVSYNC# VCDCLKIN SDO/DX LRCKO/FS0 BCKO/MCLK SDI/DR LRCKI/FS1 BCKI FSCKI UDP UDM USCKI UDP1 UDM1 HOVRCUR# HPWREN SCL[1 : 0] SDA[1 : 0] SDCKI/MSCKI SDWP/MSDIRS MSDIRP
Initial state
Core sleep mode Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation Operation HiZ HiZ Operation Operation
Bus sleep mode X or HiZ X X Operation X X X or HiZ X or HiZ X Operation Operation X or HiZ HiZ HiZ HiZ HiZ X HiZ HiZ X or HiZ X
PLL operation mode X or HiZ X X Operation X X X or HiZ X or HiZ X Operation Operation X or HiZ HiZ HiZ HiZ HiZ X HiZ HiZ X or HiZ X
PLL stop mode X or HiZ X X Operation X X X or HiZ X or HiZ X Operation Operation X or HiZ HiZ HiZ HiZ HiZ X HiZ HiZ X or HiZ X (Continued)
36
MB93461
(Continued) Pin Name SDCD/MSCD SDCMD/MSBS SDCLK/MSCLK SDDAT[0]/MSDIO[0] SDDAT[3 : 1]/MSDIO[3 : 1] SDMSSELECT Initial state Core sleep mode Operation Operation Operation Operation Bus sleep mode X or HiZ Operation X or HiZ X or HiZ PLL operation mode X or HiZ Operation X or HiZ X or HiZ PLL stop mode X or HiZ Operation X or HiZ X or HiZ
37
MB93461
HANDLING DEVICES
* Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions : * A voltage higher than VDE or lower than VSS is applied to an input or output pin. * A voltage higher than the rated voltage is applied between VDE pin and VSS pin. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, care must also be taken in not allowing the analog power-supply voltage (VDD) to exceed the digital power-supply voltage. * Handling unused pins Leaving unused input pins open may result in misbehavior or latch-up and possible permanent damage of the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k. Unused bi-directional pins should be set to the output state and can be left open, or the input state with the above described connection. When not using USB/USB-Host pin, fix both UDP1 and UDM1 to the opposite level for each other. * Power supply pins In products with multiple VDE, VDD, or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VDE, VDD, and VSS pins via the lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VDE, VDD, and VSS pins near the device. * Pull-up/down resistors The MB93461 does not support internal pull-up/down resistors (except PU/PD Pin Type) . Use external components where needed. * N.C. Pin The N.C. (internally connected) pin must be opened for use.
38
MB93461
BLOCK DIAGRAM
FR-V Digital - AV Peripherals 32-bit External memory controller FR450 core (CPU, cache) Video capture cntl Video display cntl Audio output (I2S) Audio input (I2S) MS 1.4/ SD-IO
SDRSDRAM
DSU
High bandwidth system interconnect
Bus bridge
High bandwidth system interconnect
Bus bridge Local bus interface 32-bit
DMAC GPIO I2C x2 DMAC USB 2.0 function (FS) USB 2.0 host (FS)
Low bandwidth peripheral bus
Local bus FR450 SoC Platform
Timer UART IRC GPIO
FR450 core block diagram Instruction fetch I-cache 32 KB 2-way 1RW 64 Static branch prediction Pipeline control
I I M M
Bus interface
64 MMU
64
Bypass
GR 32w x 32b 5R/3W
Integer 0 slot Integer 1 slot
32
Integer-unit 64
D-cache 32 KB 2-way 1RW Cache-unit
Bypass
FR 32w x 32b 5R/3W
Media 0 slot Media 1 slot
Media-unit
39
MB93461
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage (External) Power supply voltage (Internal) Input voltage Storage temperature Note : VSS = 0 V WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VDE VDD VI TSTG Rating Min VSS - 0.5 VSS - 0.5 VSS - 0.5 -55 Max VSS + 4.0 VSS + 1.8 VDE + 0.5 ( 4.0) + 125 Unit V V V C
40
MB93461
2. Recommended Operating Conditions
Parameter Power supply voltage (External) Power supply voltage (Internal) "L" level input voltage "H" level input voltage Operating temperature USB Parameter "H" level input voltage "L" level input voltage Differential input sensitivity Differential common mode range "H" level output voltage "L" level output voltage Output signal crossover voltage Bus pull-up/down resistor on upstream port Termination voltage on upstream port pull-up Symbol VIHU VILU VDIU VCMU VOHU VOLU VCRSU Rpu Rpd
*1 *2
[VSS = 0 V] Value Min 3.15 3.15 1.235 1.33 -0.3 2.0 0 Typ 3.3 3.3 1.3 1.4 25 Max 3.45 3.45 1.365 1.47 0.8 VDE + 0.3 70 Unit V V V V V V C [VSS = 0 V] Value Min 2.0 0.2 0.8 2.8 0.0 1.3 1.425 14.25 3.15 Typ Max 0.8 2.5 3.45 0.3 2.0 1.575 15.75 3.45 Unit V V V V V V V k k V
Symbol VDE VDDI 360 MHz 400 MHz 360 MHz 400 MHz VIL VIH Ta
VTERM
*1 : If USB function is used , it is necessary to attach "Rpu" outside to D+ or D-. *2 : If USB host is used , it is necessary to attach "Rpd" outside to D+ and D-. Notes : Board Wiring * For connecting the power supply and ground (GND) , use multiple VDD and VSS pins. The system board based on the MB93461 must be a multi-layer board containing power supply (VDD) and GND (VSS) layers for stable power supply. * Insert sufficient decoupling capacitors (condensers) near the MB93461. Changes to the output levels of many of the output pins on the MB93461 (in particular, those with large load capacitance) may cause variation in power supply. * For those systems which run at a high frequency, low-inductance capacitors and mutual wiring are recommended. Inductance can be lowered by shortening the distance between the processor and decoupling capacitor. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 41
MB93461
3. DC Characteristics
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] Value Symbol Condition Unit Min Typ Max VIL VIH VOL VOH ILI ILZ 360 MHz IDE 400 MHz IOL = 100 A IOH = -100 A VIN = 0 or VDE VOUT = 0 or VDE CMODE = 0x3, CLKIN = 60 MHz, (Dhrystone2.1 + DMA transfer) No Load CMODE = 0x3, CLKIN = 66MHz, (Dhrystone2.1 + DMA transfer) No Load 0 2.0 0 VDE - 0.2 -5 -5 0 40 0.8 VDE 0.2 VDE 5 5 V V V V A A mA
Parameter "L" level input voltage "H" level input voltage "L" level output voltage "H" level output voltage Input leakage current Tri-state output leakage current
80
Power supply current (VDE)
0
44
88
mA
Power supply current (VDD)
IDD
360 CMODE = 0x3, CLKIN = 60 MHz, MHz (Dhrystone2.1 + DMA transfer) 400 CMODE = 0x3, CLKIN = 66 MHz, MHz (Dhrystone2.1 + DMA transfer) 360 Core sleep mode, MHz CLKIN = 60 MHz 400 Core sleep mode, MHz CLKIN = 66 MHz 360 Bus sleep mode, MHz CLKIN = 60 MHz 400 Bus sleep mode, MHz CLKIN = 66 MHz 360 PLL On mode, MHz CLKIN = 60 MHz 400 PLL On mode, MHz CLKIN = 66 MHz PLL Stop mode, CLKIN = 0 MHz VDE = VI = 0, f = 1 MHz
196 245 70 87 32.4 40.6 18.2 22.4 5
420 520 16
mA mA mA mA mA mA mA mA mA pF
ICORESLEEP
At sleep power supply current
IBUSSLEEP
IPLLON
IPLLOFF Capacity of pins CPIN
42
MB93461
USB [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] Value Symbol Conditions Unit Min Typ Max VOL VOH IOL IOH IOS IOL = 20 mA IOH = -20 mA VOL = 0.4 V VOH = VDE - 0.4 V 0 VDE - 0.5 20 -20 0.4 VDE 300 V V mA mA mA
Parameter "L" level output voltage "H" level output voltage "L" level output current "H" level output current
Output short-circuit current I2C
Parameter "L" level input voltage "H" level input voltage
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] Value Symbol Conditions Unit Min Typ Max VIL VIH VOL1 VHYS II IOL = 3 mA -0.5 0.7 x VDE 0 0.05 x VDE -10 0.3 x VDE VDE 0.4 10 V V V V A
"L" level output voltage 1 Schmitt trigger hysteresis Data line leakage
43
MB93461
4. AC Characteristics
(1) Local Bus Interface [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz 400 MHz Reference Unit Item Parameter Signal Min Max Min Max CLKIN period (TCLKIN) CLKIN high time CLKIN input CLKIN low time CLKIN rise time CLKIN fall time BGNT# A [31 : 2] D [31 : 0] BE/BE# [0 : 3] BS# RD# Local-bus I/F output WE# DIR RDY# CS# [3 : 0] CS# [7 : 4]/ IRQ# [7 : 4] BSTREQ# BSTACK# Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output hold time Output hold time Output hold time Output hold time CLKIN rise CLKIN rise CLKIN rise CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN fall Output valid delay time CLKIN rise Output hold time Output hold time CLKIN rise CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output hold time Output hold time Output hold time CLKIN rise CLKIN rise CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise 15* 6.0 6.0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 27* 1.0 1.0 6.5 6.5 6.5 6.5 6.5 6.5 7.0 6.5 6.5 6.5 6.5 6.5 6.5 15* 6.0 6.0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.0 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 23.5* 1.0 1.0 6.5 6.5 6.5 6.5 6.5 6.5 7.0 6.5 6.5 6.5 6.5 6.5 6.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Continued)
* : Refer to "5. Clock Setting" for details.
44
MB93461
(Continued) [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360MHz 400MHz Reference Parameter Unit Signal Min Max Min Max BREQ# A [31 : 2] D [31 : 0] BE/BE# [0 : 3] BS# DIR Local-bus I/F input RDY# ERR# CS# [7 : 4]/ IRQ# [7 : 4] IBW BSTREQ# BSTACK# Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Item
Notes : * Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise noted. Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V, the input level is 0.4 V to 2.4 V, and the input rise time and fall time are 1.5 ns or less. The external output load capacitance is 30 pF. * Maximum frequency of CLKIN varies depending on the setting of CMODE [0] to [3] pins. Please refer to " 5. Clock Setting."
45
MB93461
Setup Hold
Valid
Valid
Hold
Hold
CLKIN
Input pin
Output pin
Input-and-output pin
WE#
46
MB93461
(2) SDRAM Interface [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz 400 MHz Reference Parameter Unit Signal Min Max Min Max DCLKFB period (TDCLKFB) DCLKFB high time DCLKFB input DCLKFB low time DCLKFB rise time DCLKFB fall time DBA [1 : 0] DA [12 : 0] DRAS# SDRAM I/F output DCAS# DWE# DCKE 7.5* 2.5 2.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 20* 1.0 1.0 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 7.5* 2.5 2.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 17.5* 1.0 1.0 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Item
DCS# [3 : 0] Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output valid delay time DCLKFB rise Output hold time Input setup time Input hold time DCLKFB rise DCLKFB rise DCLKFB rise
DDQM [0 : 3] Output valid delay time DCLKFB rise DDQ [31 : 0] SDRAM I/F input DDQ [31 : 0]
* : This value is decided by CMODE. Notes : * Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise noted. Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V, the input level is 0.4 V to 2.4 V, and the input rise time and fall time are 1.5 ns or less unless otherwise noted. The external output load capacitance is 30 pF unless otherwise noted. * The frequency of the input to DCLKFB and the output from DCLK is decided by the input frequency to CLKIN, and setup of a CMODE [3 : 0] pins. Refer to "5. Clock Setting" for details.
Setup Hold Valid Hold
DCLKFB
Output pin
Input-andoutput pin
47
MB93461
* This LSI outputs DCLK which is supplied to SDRAM as a clock. PLL is built into this LSI. Adjust the phase of DCLK so that the CLK pin of SDRAM and the internal phase in this LSI may be nearly equal. Therefore, when connecting, adjust the delay time of the feedback path from DCLK to DCLKFB, so that the phase of the clock input to DCLKFB which is the feedback signal to PLL and the phase of the clock (wave shape on the reception edge of DCLK) input to CLK of SDRAM may be nearly equal.
48
MB93461
(3) General-purpose Peripheral Resource [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz 400 MHz Reference Item Parameter Unit Signal Min Max Min Max IRQ# [3 : 0]/ PP [03 : 00] TOUT[0]/ GATE[0]/ PP[04] TOUT[1]/ GATE[1]/ PP[05] RXD[0]/ PP[06] TXD[0]/PP[07] CTS# [0]/ PP[08] RST# [0]/ PP[09] Resources RXD[1]/ output PP[10] TXD[1]/PP[11] DREQ# [0]/ PP[12] DACK# [0]/ PP[13] DONE# [0]/ DREQ# [4]/ PP[14] DREQ# [1]/ PP[15] DACK# [1]/ PP[16] DONE# [1]/ DREQ# [5]/ PP[17] Output valid delay time CLKIN rise Output hold time CLKIN rise Output valid delay time CLKIN rise Output hold time CLKIN rise 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Continued)
Output valid delay time CLKIN rise Output hold time CLKIN rise
Output valid delay time CLKIN rise Output hold time Output hold time Output hold time Output hold time Output hold time Output hold time Output hold time Output hold time CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output hold time CLKIN rise
Output valid delay time CLKIN rise Output hold time Output hold time CLKIN rise CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output hold time CLKIN rise
49
MB93461
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz 400 MHz Reference Parameter Unit Signal Min Max Min Max DREQ#[2]/ PP[18] DREQ#[3]/ PP[19] Resources DACK#[2]/ output DREQ#[6]/ PP[20] DACK#[3]/ DREQ#[7]/ PP[21] IRQ#[3 : 0]/ PP [03 : 00] TOUT[0]/ GATE[0]/ PP[04] TOUT[1]/ GATE[1]/ PP[05] RXD[0]/ PP[06] TXD[0]/PP[07] Resources CTS#[0]/ input PP[08] RST#[0]/ PP[09] RXD[1]/ PP[10] TXD[1]/PP[11] DREQ#[0]/ PP[12] DACK#[0]/ PP[13] Output valid delay time CLKIN rise Output hold time Output hold time CLKIN rise CLKIN rise Output valid delay time CLKIN rise Output valid delay time CLKIN rise Output hold time CLKIN rise 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 10.0 10.0 10.0 10.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 10.0 10.0 10.0 10.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Continued)
Item
Output valid delay time CLKIN rise Output hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise
50
MB93461
(Continued) [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz 400 MHz Reference Parameter Unit Signal Min Max Min Max DONE#[0]/ DREQ#[4]/ PP[14] DREQ#[1]/ PP[15] DACK#[1]/ PP[16] DONE#[1]/ DREQ#[5]/ Resources PP[17] input DREQ#[2]/ PP[18] DREQ#[3]/ PP[19] DACK#[2]/ DREQ#[6]/ PP[20] DACK#[3]/ DREQ#[7]/ PP[21] Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise CLKIN rise 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 4.0 1.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Item
Note : Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise noted. Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V, the input level is 0.4 V to 2.4 V, and the input rise time and fall time are 1.5 ns or less. The external output load capacitance is 30 pF unless otherwise noted.
Setup Hold
Valid
Hold
CLKIN
Input pin
Output pin
Input-andoutput pin
51
MB93461
(4) ICE Interface [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz 400 MHz Reference Parameter Unit Signal Min Max Min Max ECLK output period ECLK output high time ECLK output ECLK output low time ECLK output rise time ECLK output fall time ICE output ED ERST# Output valid delay time Output hold time Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time ECLK rise ECLK rise ECLK rise ECLK rise ECLK rise ECLK rise ECLK rise ECLK rise 30 13.0 13.0 0.0 5.0 0.0 16 5.0 0.0 5.0 0.0 2.0 2.0 8.0 30 13.0 13.0 0.0 5.0 0.0 16 5.0 0.0 5.0 0.0 2.0 2.0 8.0 ns ns ns ns ns ns ns ns ns TCLKIN* ns ns ns ns
Item
HRST# Low pulse width ICE input ECV ED
* : Unit of TCLKIN is CLKIN period. Please refer to "4. (1) Local Bus Interface". Note : Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise noted. Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V, and the input level is 0.4 V to 2.4 V. The input rise time and fall time are 1.5 ns or less. The external output load capacitance is 30 pF unless otherwise noted.
Setup Hold
Valid
Hold
ECLK
Input pin Input-and -output pin
52
MB93461
(5) Reset-related Pin [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz 400 MHz Reference Parameter Unit Signal Min Max Min Max RSTOUT# PRST# RAMBOOT# Output valid delay time Low pulse width Low pulse width CLKIN rise 0 16 16 8.0 0 16 16 8.0 ns TCLKIN* TCLKIN*
Item Reset output Reset input Boot input
* : Unit of TCLKIN is CLKIN period. Please refer to "4. (1) Local Bus Interface". (6) CPU Status [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz 400 MHz Reference Parameter Unit Signal Min Max Min Max CPUHOLD Output valid delay time CLKIN rise 0 8.0 0 8.0 ns
Item CPU output (7) Clock
Item
[360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz 400 MHz Reference Parameter Unit Signal Min Max Min Max Input setup time Input hold time Must be fixed to "H" or "L" Must be fixed to "H" or "L"
Clock mode input CMODE[3 : 0]
(8) Test [360 MHz : VDE = 3.3 V 0.15, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz 400 MHz Reference Parameter Unit Signal Min Max Min Max TESTMODE Test mode input TDC MTESTMODE Input setup time Input hold time Input setup time Input hold time Input setup time Input hold time Must be fixed to "L" Must be fixed to "L" Must be fixed to "L" Must be fixed to "L" Must be fixed to "L" Must be fixed to "L"
Item
53
MB93461
(9) Video Display Controller (VDC) [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz/400 MHz Reference Item Parameter Unit Signal Min Max VDPCLKIN period VDC clock input VDPCLKIN high time VDPCLKIN low time VDR [7 : 0]/VDCR [7 : 0] VDG [7 : 0]/VDY [7 : 0]/ VDX[7 : 0] Output hold time Output valid delay time VDCLKOUT fall VDCLKOUT fall 12.5 4 4 -2 -2 -2 -2 -2 -2 -2 -2 -2 7 2.5 1.5 125 3 3 3 3 3 3 3 11 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Output valid delay time VDCLKOUT fall
VDB [7 : 0]/VDCX[7 : 0]/ Output valid delay time VDCLKOUT fall VDCB [7 : 0] Output hold time VDCLKOUT fall VDC I/F output VDHSYNC/ VDHSYNC# VDVSYNC/ VDVSYNC# ENABLE/ENABLE# TOPFIELD/ TOPFIELD# VDCLKOUT* VDC I/F input DISABLE Output valid delay time VDCLKOUT fall Output valid delay time VDCLKOUT fall Output valid delay time VDCLKOUT fall Output valid delay time VDCLKOUT fall Output valid delay time VDPCLKIN rise Input setup time Input hold time VDPCLKIN rise VDPCLKIN rise
* : The falling edge of VDCLKOUT is synchronous with respect to the rising edge of VDPCLKIN. Note : Each parameter is valid within the specified ranges of temperature and supply voltage unless otherwise noted. Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V, and the input level is 0.4 V to 2.4 V. The external output load capacitance is 15 pF.
54
MB93461
(10) Video Capture Controller (VCC) [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz/400 MHz Reference Item Parameter Unit Signal Min Max VCDCLKIN period VCC clock input VCDCLKIN high time VCDCLKIN low time VCR [7 : 0]/VCCR [7 : 0] VCG[7 : 0]/VCY[7 : 0]/ VCX[7 : 0] VCC I/F input Input setup time Input hold time Input setup time Input hold time VCDCLKIN edge* VCDCLKIN edge* VCDCLKIN edge* VCDCLKIN edge* VCDCLKIN edge* VCDCLKIN edge* VCDCLKIN edge* VCDCLKIN edge* VCDCLKIN edge* VCDCLKIN edge* 12.5 4 4 2.5 1.5 2.5 1.5 2.5 1.5 2.5 1.5 2.5 1.5 125 ns ns ns ns ns ns ns ns ns ns ns ns ns
VCB[7 : 0]/VCCX[7 : 0]/ Input setup time VCCB[7 : 0] Input hold time VCHSYNC/ VCHSYNC# VCVSYNC/ VCVSYNC# Input setup time Input hold time Input setup time Input hold time
*: The reference signal of VCC interface is decided by the setting of register in the VCC unit. RCC.ES = 0 : falling edge of VCDCLKIN RCC.ES = 1 : rising edge of VCDCLKIN Please refer to MB93461 LSI specification. Note : Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise noted. Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V, and the input level is 1.0 V to 2.0 V. The external output load capacitance is 30 pF.
55
MB93461
(11) Audio [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz/400 MHz Reference Parameter Unit Signal Min Max FSCKI period FSCKI high time Audio clock input FSCKI low time BCKI period BCKI high time BCKI low time SDO* Audio I/F output LRCKO* BCKO* LRCKI SDI Audio I/F input LRCKI Output valid delay time Output valid delay time Output valid delay time Output valid delay time Input setup time Input hold time Input setup time Input hold time FSCKI rise FSCKI rise FSCKI rise FSCKI rise BCKI rise BCKI rise BCKI rise BCKI rise 25 10.5 10.5 100 42 42 3 3 3 3 15 15 15 15 11 11 11 11 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Item
* : LRCKO and SDO signals are generated with respect to the falling edge of BCKO (duty 50%) . Note : Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise noted. Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V, and the input level is 0.4 V to 2.4 V. The external output load capacitance is 30 pF.
56
MB93461
(12) USB Interface [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz/400 MHz Reference Parameter Unit Signal Min Max USCKI period USB clock input USCKI high time USCKI low time D+/D- rise time USB driver D+/D- fall time Driver output resistance TFR TFF 20 8 8 4 4 90 28 20 20 111.11 44 ns ns ns ns ns %
Item
Differential rise and fall time matching
Notes : * Frequency of USCKI is set to 48 MHz in order to carry out operation based on the standard of USB 2.0 FS. Furthermore, it is necessary to put in a clock with a frequency accuracy of 2500 ppm. * In order to fulfill the standard of USB 2.0 FS, it is necessary to add 25 to 30 in-series resistance outside.
D+
90%
90%
10%
10% TFR TFF
D-
57
MB93461
(13) I2C [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz/400 MHz Reference Parameter Unit Signal Min Max SCL[1 : 0] I2C I/F output SDA[1 : 0] Output fall time Output rise time Output fall time Output rise time 23* 23* 23* 23* 250 300 250 300 ns ns ns ns
Item
* : 20 + 0.1 x C (C = Capacitance of one bus line in pF) Notes : * Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise noted. * Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V, the input level is 0.4 V to 2.4 V, and the input rise time and fall time are 1.5 ns or less. * The external output load capacitance is 30 pF. (14) GPIO [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz/400 MHz Reference Parameter Unit Signal Min Max AVPP[39 : 8] AVPP[39 : 8] Output valid delay time Output hold time Input setup time Input hold time ns ns ns ns
Item GPIO I/F output GPIO I/F input
Notes : * AVPP[39 : 8] is an asynchronous pin. * Each parameter is valid within the specified ranges of temperature and supply voltages unless otherwise noted. Each voltage value is based on the GND (VSS = 0.0 V) level. The timing measurement reference point is 1.5 V, and the input level is 0.4 V to 2.4 V. The external output load capacitance is 30 pF. (15) Memory Stick Interface Note : Customers are advised to consult with our sales representatives , if you use MS. (16) SD-IO Interface Note : Customers are advised to consult with our sales representatives , if you use SD.
58
MB93461
(17) Power Sequence [360 MHz : VDE = 3.3 V 0.15 V, VDD = 1.3 V 0.065 V, VSS = 0 V, Ta = 0 C to + 70 C] [400 MHz : VDE = 3.3 V 0.15 V, VDD = 1.4 V 0.07 V, VSS = 0 V, Ta = 0 C to + 70 C] 360 MHz/400 MHz Reference Parameter Unit Signal Min Max VDE rise time Power-on VDD rise time Delay time from VDE rise to VDD rise Note : Power-off Sequence is not defined. * Power-on Sequence TRE TRD TDRED -100 30 15 100 ms ms ms
Item
VDE
TRE
VDE-Min
TDRED VDD-Min
VDD
TRD
59
MB93461
5. Clock Setting
In this LSI, the clock signal inputted into CLKIN is multiplied by internal PLL, and it has distributed to each part in LSI. The multiplication rate for each clock is decided using the CMODE [3 : 0] pins. Depending on this setup, the maximum frequency of CLKIN may be restricted. The maximum frequency that can be inputted into CLKIN and the frequency of each part of LSI are shown below. CLKIN input CMODE [0] to [3] Ratio CLKIN Freq. Internal operating clock of this LSI 360 MHz or 400 MHz 360 MHz 400 MHz 360 MHz 400 MHz 360 MHz 400 MHz 360 MHz 400 MHz 360 MHz 400 MHz Period (TCLKIN) [ns] Min Max Freq. [MHz] Min Max
3210
External bus
SDRAM
Core bus
Core
DSU
15.0 18.0 55.6 66.7 15.0 15.5 64.5 66.7 15.0 20.0 50.0 66.7 15.0 17.5 57.1 66.7 16.7 20.0 50.0 60.0 15.0 17.5 57.1 66.7 16.7 20.0 50.0 60.0 15.0 17.5 57.1 66.7 15.0 18.0 55.6 66.7 15.0 15.5 64.5 66.7
0000
Ratio
x1
x1
x1
x1
x1
x0.5
0001
Ratio
x1
x1
x1
x1
x3
x0.25
0010
Ratio
x1
x1
x1
x2
x6
x0.5
0011
Ratio
x1
x1
x2
x2
x6
x0.5
0100
Ratio
x1
x1
x1
x2
x2
x0.16
0101 0110 0111
Reserved Reserved Reserved 360 MHz 400 MHz 15.0 18.0 55.6 66.7 15.0 15.5 64.5 66.7 (Continued)
1000
Ratio
x1
x1
x1
x1
x2
x0.16
60
MB93461
(Continued) CLKIN input CMODE [0] to [3] Ratio CLKIN Freq. Internal operating clock of this LSI 360 MHz or 400 MHz 360 MHz 400 MHz Period (TCLKIN) [ns] Min Max Freq. [MHz] Min Max
3210
External bus
SDRAM
Core bus
Core
DSU
15.0 18.0 55.6 66.7 15.0 15.5 64.5 66.7
1001
Ratio
x1
x1
x2
x2
x4
x0.33
1010 1011
Reserved Reserved 360 MHz 400 MHz 360 MHz 400 MHz 360 MHz 400 MHz 15.0 18.0 55.6 66.7 15.0 15.5 64.5 66.7
1100
Ratio
x1
x1
x1
x2
x4
x0.33
1101
Reserved 25.0 27.0 37.0 40.0 22.5 23.5 42.6 44.4 15.0 20.0 50.0 66.7 15.0 17.5 57.1 66.7
1110
Ratio
x1
x1
x3
x3
x9
x0.75
1111
Ratio
x1
x1
x1.5
x1.5
x4.5
x0.375
Notes : * "x" indicates the frequency ratio for the external input clock. * By default, the operating frequency of the resource bus clock is the same as that of the external bus. * When CLKC.p0 is set to "1", the operating frequency of the resource bus clock is half that of the external bus. However, the frequency of the resource bus clock is fixed to 1/2 operating frequency of the external bus when CMODE = F regardless of the setting of CLKC.p0. * As the setting of CMODE = 5, 6, 7, A, B, D that is the hatched part in the table is not confirmed for operation guarantee, do not set them.
61
MB93461
CONNECTION WITH MEMORY
1. Connection with ROM or SRAM
An example of connection between this processor and ROM or SRAM, etc. is shown below. Example : Four SRAMs (each of "256 K x 8 bits") are connected to the 32-bit bus (The polarity of BE/BE# is positive logic) .
MB93461
A [19:2] D [31:24] DIR WE# CS# [n] BE [0]/BE# [0]
A [17:0] I/O [7:0] OE# WE# CS1# CS2 SRAM (1)
A [17:0] D [23:16] I/O [7:0] OE# WE# CS1# BE [1]/BE# [1] CS2 SRAM (2)
A [17:0] D [15:8] I/O [7:0] OE# WE# CS1# BE [2]/BE# [2] CS2 SRAM (3)
A [17:0] D [7:0] I/O [7:0] OE# WE# CS1# BE [3]/BE# [3] CS2 SRAM (4)
RDY#
62
MB93461
2. Connection with SDRAM
SDRAM can be connected directly to DCS# [0] or DCS# [1]. An example in which two SDRAMs (each of "1 M x 4 banks x 16 bits") are connected to the 32-bit bus is shown below.
MB93461
DBA [1:0] DA [11:0] DCS# [0] DRAS# DCAS# DWE# DDQM [0:1] DDQ [31:16] DCKE DCLK DCLKFB
BA [1:0] A [11:0] CS# RAS# CAS# WE# DQMU, L DQ [15:0] CKE CLK
SDRAM (1)
BA [1:0] A [11:0] CS# RAS# CAS# WE# DDQM [2:3] DDQ [15:0] DQMU, L DQ [15:0] CKE CLK
SDRAM (2)
Note : This LSI outputs DCLK which is supplied to SDRAM as a clock. PLL is built into this LSI. Adjust the phase of DCLK so that the CLK pin of SDRAM and the internal phase in this LSI may be nearly equal. Therefore, when connecting, adjust the delay time of the feedback path from DCLK to DCLKFB, so that the phase of the clock input to DCLKFB which is the feedback signal to PLL and the phase of the clock (wave shape on the reception edge of DCLK) input to CLK of SDRAM may be nearly equal.
63
MB93461
Example : Connecting Registered-DIMM to DCS#[3 : 2] DCS#[2] and DCS#[3] are only used for connecting the 168-pin registered DIMM. Connect the 168-pin registered DIMM as follows. The DIMM must be "registered". In the registered DIMM, it is assumed that the module connected to DCS#[2] or DCS#[3] is used after DCS#, DBA, DA, DRAS#, DCAS#, DWE#, DDQM, and DCKE are latched once at the rising of DCLK signal. When using DCS#[2] or DCS#[3], the bus width must be set to the 32-bit mode.
MB93461
168-pin Registered-DIMM
DBA [1:0] DA [12:0] DCS# [2] DCS# [3] DRAS# DCAS# DWE# DDQM [0:1] BA [1:0] A [12:0] S0# S2# RAS# CAS# WE# DQMB [4:5] DQMB [6:7] DDQM [2:3] DQMB [0:1] DQMB [2:3] DDQ [31:16] DQ [47:32] DQ [63:48] DDQ [15:0] DQ [15:0] DQ [31:16] DCKE DCLK DCLKFB CKE CLK
64
MB93461
CONNECTION WITH PERIPHERAL DEVICE
1. Connection with MB93441 (PCI Bridge Chip)
An example of connection between this processor and peripheral device is shown below.
Clock Gen. MB93461 CLKIN BREQ# BGNT# D[31:00] A[27:2] BE[0:3] DIR CLKIN BREQ# BGNT# D[31:00] A[27:2] BE[0:3] DIR MB93441
BS# RDY#
BS# RDY#
DREQ#[n] (n : 0 to 7)
Correspondence is arbitrary.
DREQ# CSC#
CS#[n] (n : Arbitrary except 0) IRQ[n]/PP[n] (n : 0 to 3) BSTREQ#
Correspondence is arbitrary.
CSR# IRQ# BSTREQ#
Correspondence is arbitrary.
BSTACK#
BSTACK#
PRST#
PRST#
BW16 Reset Gen.
65
MB93461
2. Connection with MB93443 (IDE/PC-Card Host Controller)
An example of connection between this processor and peripheral device is shown below.
Clock Gen. MB93461 CLKIN CLKIN MB93443
D[31:00] A[15:2] BE[0:3] DIR
D[31:00] A[15:2] BE[0:3] DIR
BS# RDY#
BS# RDY#
DREQ#[n] (n : 0 to 7)
Correspondence is arbitrary.
DREQ# CSC#
CS#[n] (n : Arbitrary except 0) IRQ[n]/PP[n] (n : 0 to 3) BSTREQ#
Correspondence is arbitrary.
CSR# IRQ# BSTREQ#
Correspondence is arbitrary.
BSTACK#
BSTACK#
PRST#
PRST#
BW16 Reset Gen.
66
MB93461
PACKAGE DIMENSIONS
420-ball plastic BGA (BGA-420P-M25)
27.000.20(1.063.008) 24.00 +0.70 .945 -.002 -0.05
+.028
25.00(.984)BSC
4-C2.0 (4-C.079 )
0.50(.020) BSC
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AF AE AD AC AB AA Y WV U T R P N M L K J H G F E D C B A
27.000.20 (1.063.008) 24.00 -0.05 +.028 .945 -.002
+0.70
4X10.00 (4X.394)
0.50(.020) BSC
25.00(.984) BSC 1.00(.039) BSC
1 PIN INDEX 0.35(.014) C 0.15(.006) C C SEATING PLANE
3-R0.5 (3-R.020)
A
o0.630.15(.025.006) 0.30(.012) M C A B 0.10(.004) M C
B
0.25(.010) C
0.560.06 (.022.002) 0.500.10 (.020.004)
2.230.21 (.088.008) 1.170.05 (.046.002)
C
2005 FUJITSU LIMITED BGA420025Sc-1-2
Dimensions in mm (inches). Note: The values in parentheses are reference values.
400-ball plastic PFBGA (BGA-400P-M04)
15.000.10(.591.004) 0.20(.008) S B 14.00(.551)REF B 0.50(.020) TYP
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AJ AH J GECA AG AE AC AA W U R N L V T PMK HF DB AF AD AB Y
A 15.000.10 (.591.004) 14.00(.551) REF 0.50(.020) TYP
(INDEX AREA) S
0.20(.008) S A 481-o0.300.10 (481-o.012.004)
o0.05(.002)
M
INDEX SAB
0.15(.006) S
0.250.10 (.010.004) (Stand off)
1.150.20 (.045.008) (Seated height)
C
2004 FUJITSU LIMITED B400004S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values.
67
MB93461
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0504 (c) 2005 FUJITSU LIMITED Printed in Japan

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